As integrated circuits operate at higher frequencies, the integrated circuit design must account for signal loss caused by impedance mismatch due to packaging. One method of transferring a signal between a die and a substrate is the use of wire bonds. However, wire bonds used in signal transfer are inductive and thereby result in higher impedance mismatch at higher frequencies. Thus, an off-chip matching circuit which is capacitive in nature is generally used.
For example, a single ended wire bond interface may be used to connect a single wire bond or multiple wire bonds between a single die bond pad and a single lead on the package. The single lead on the package connects to a single microstrip line. The single ended wire bond approach results in an inductance created by the overall wire bond length. This approach requires an off-chip matching circuit which is capacitive to match the die impedance, of which wire bond inductance is a component. However, at higher frequencies the inductive reactance due to wire length increases, thereby requiring a higher capacitance in the off-chip match. This leads to higher Quality factor and subsequently lower bandwidth. Consequently, a lower bandwidth makes the circuit less tolerant to manufacturing variations.
Additionally, integrated circuits that operate at high frequencies, for example 15 GHz or above, present certain design considerations. The reactance created at 15 GHz or above is more than the reactance created when operating at lower frequencies. The increase in reactance when operating at high frequencies results in a need to balance with increased capacitive off-chip matching circuitry. At present, the difficulty of impedance matching at high frequencies results in increased signal loss and an increase in return loss.
Another method of transferring a signal between a die and a substrate, that addresses the issue of impedance matching at high frequencies, is the use of flip-chip technology. The flip-chip approach involves, for example, growing a copper pillar on a die, and then connecting the die upside down to the substrate. This method results in a shorter connection, and therefore less inductance. One of the benefits of this method is that lower inductance can be managed in integrated circuit design more easily. However, the flip-chip approach presents challenges of heat dissipation when using higher power, which raises junction temperature on the die. Different measures have been taken to manage this thermal issue but there is a limit to the effectiveness and the practicality of these measures.
Thus, there is a need for internal matching of impedance on an integrated circuit that operates at high frequencies and accommodates thermal dissipation and manufacturing tolerance limitations. The invention addresses this and other needs.